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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad10200 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 dual channel, 12-bit 105 msps if sampling a/d converter with analog input signal conditioning functional block diagram 50 d00b (lsb) 49 d01b 48 d02b 47 d03b 46 d04b 45 d05b 42 d06b 41 d07b 40 d08b 39 d09b 38 d10b 37 d11b (msb) 34 d00a (lsb) d01a d02a d03a d04a d05a d06a d07a d08a d09a d10a d11a (msb) 21 33 32 31 30 29 28 25 24 23 22 adc 7 50 a in a2 t1a adc 63 50 a in b2 t1b ad10200 output resistors 12 12 18 17 encodea encodea ref 3 ref_a_out timing 53 54 encodeb encodeb ref 56 ref_b_out output resistors 12 12 t/h t/h timing features dual, 105 msps minimum sample rate channel-channel isolation, >80 db ac-coupled signal conditioning included gain flatness up to nyquist: < 0.2 db input vswr 1.1:1 to nyquist 80 db spurious-free dynamic range twos complement output format 3.3 v or 5 v cmos-compatible output levels 0.850 w per channel industrial and military grade applications radar if receivers phased array receivers communications receivers secure communications gps antijamming receivers multichannel, multimode receivers product description the ad10200 is a full channel adc solution with on-module signal conditioning for improved dynamic performance and fully m atched channel-to-channel performance. the module includes two wide-dynamic range adcs. each adc has a transformer coupled front-end optimized for direct-if sampling. the ad10200 has on-chip track-and-hold circuitry, and utilizes an innovative architecture to achieve 12-bit, 105 msps perfor- mance. the ad10200 uses innovative high-density circuit design to achieve exceptional matching and performance while still maintaining excellent isolation, and providing for significant board area savings. the ad10200 operates with 5.0 v supply for the analog-to- digital conversion. each channel is completely independent allowing operation with independent encode and analog inputs. the ad10200 is packaged in a 68-lead ceramic chip carrier package. manufacturing is done on analog devices, inc. mil- 38534 qualified manufacturers line (qml) and components are available up to class-h (?5 c to +125 c). product highlights 1. guaranteed sample rate of 105 msps. 2. input signal conditioning with full power bandwidth to 250 mhz. 3. fully tested/characterized performance at 121 mhz a in . 4. optimized for if sampling.
rev. a C2C ad10200?pecifications 1 (v dd = 3.3 v, v cc = 5.0 v; encode = 105 msps, unless otherwise noted) test mil parameter temp level subgroup min typ max unit resolution 12 bits dc accuracy differential nonlinearity full iv 12 ?.99 0.5 +0.99 lsb integral nonlinearity full iv 12 ? 0.75 +3 lsb no missing codes full i 1, 2, 3 guaranteed gain error 2 full i 1, 2, 3 9 1+9% fs output offset full i 1, 2, 3 ?2 +12 lsb analog input input voltage range 25 c v 2.048 v p-p input impedance 25 cv 50 ? input vswr 3 full iv 12 1.1:1 1.25:1 ratio analog input bandwidth, high full iv 12 200 250 mhz analog input bandwidth, low full iv 12 1 mhz analog reference output voltage full i 1, 2, 3 2.4 2.5 2.6 v load current 25 cv 5 ma tempco full v 50 ppm/ c switching performance maximum conversion rate full i 4, 5, 6 105 msps minimum conversion rate full iv 12 10 msps duty cycle full iv 12 45 50 55 % aperture delay (t a )25 c v 1.0 ns aperture uncertainty (jitter) 25 c v 0.25 ps rms output valid time (t v ) 4 full iv 12 3.0 5.3 ns output propagation delay ( pd ) 4 full iv 12 4.5 5.5 8.0 ns output rise time (t r )25 c v 12 3.5 ns output fall time (t f )25 c v 12 3.3 ns digital inputs encode input common mode full iv 12 1.2 1.6 2.0 v differential input (enc, enc ) full iv 12 0.4 5.0 v logic ??voltage full iv 12 2.0 v logic ??voltage full iv 12 0.8 v input resistance full iv 12 358k ? input capacitance 25 c v 4.5 pf digital outputs logic ??voltage 4 full vi 1, 2, 3 3.1 3.3 v logic ??voltage 4 full vi 1, 2, 3 0 0.2 v output coding two? complement power supply 5 power dissipation 6 full i 1, 2, 3 1800 2200 mw power supply rejection ratio full iv 12 0.5 5 mv/v i (dv dd ) current full i 1, 2, 3 25 40 ma i (av cc ) current full i 1, 2, 3 340 410 ma dynamic performance signal-to-noise ratio (snr) 7 (without harmonics) f in = 10 mhz 25 c v 67 dbfs full v 66 dbfs f in = 41 mhz 25 c i 4 64 66.5 dbfs full ii 5, 6 62 65 dbfs f in = 71 mhz 25 c i 4 62.5 66.4 dbfs full ii 5, 6 61.5 64 dbfs f in = 121 mhz 25 c i 4 61 65 dbfs full ii 5, 6 61 64 dbfs
rev. a C3C ad10200 test mil parameter temp level subgroup min typ max unit dynamic performance (continued) signal-to-noise ratio (sinad) 8 (with harmonics) f in = 10 mhz 25 c v 66 dbfs full v 63 dbfs f in = 41 mhz 25 c i 4 63 65.5 dbfs full ii 5, 6 60.5 63 dbfs f in = 71 mhz 25 c i 4 61 63.5 dbfs full ii 5, 6 57 60 dbfs f in = 121 mhz 25 c i 4 56 58.5 dbfs full ii 5, 6 53 55 dbfs spurious free dynamic range 9 f in = 10 mhz 25 c v 81 dbfs full v 70 dbfs f in = 41 mhz 25 c i 4 73 81 dbfs full ii 5, 6 67.5 dbfs f in = 71 mhz 25 c i 4 67 74 dbfs full ii 5, 6 60 dbfs f in = 121 mhz 25 c i 4 61 65 dbfs full ii 5, 6 55.5 58 dbfs two-tone intermodulation distortion 10 (imd) f in = 10 mhz; f in = 12 mhz 25 c v 86 dbc full v 81 dbc f in = 71 mhz; f in = 72 mhz 25 c v 70 dbc full v 65 dbc f in = 121 mhz; f in = 122 mhz 25 c i 4 55.5 62 dbc full ii 5, 6 53 57 dbc channel-to-channel isolation 11 f in = 121 mhz full iv 12 80 85 db notes 1 all ac specifications tested by driving encode and encode differentially. 2 gain error measured at 2.5 mhz. 3 input vswr guaranteed 10 mhz to 200 mhz. 4 t v and t pd are measured from the transition points of the encode input to the 50%/50% levels of the digital outputs swing. the digital ou tput load during test is not to exceed an ac load of 10 pf or a dc current of 40 ma. 5 supply voltages should remain stable within 5% for normal operation. 6 power dissipation measured with encode at rated speed and 0 dbm analog input. 7 analog input signal power at ? dbfs; signal-to-noise ratio (snr) is the ratio of signal level to total noise (first 5 harmonic removed). encode = 105 msps. snr is reported in dbfs, related back to converter full scale. 8 analog input signal power at ? dbfs; signal-to-noise and distortion (sinad) is the ratio of signal level to total noise + harm onics. encode = 105 msps. sinad is reported in dbfs, related back to converter full scale. 9 analog input signal equal ? dbfs; sfdr is ratio of converter full scale to worst spur. 10 both input tones at ? dbfs; two tone intermodulation distortion (imd) rejection is the ratio of either tone to the worst third order intermod product. f1 = x mhz 100 khz, f2 = x mhz 100 khz. 11 channel-to-channel isolation tested with a channel/50 ? terminated (a in a2) grounded and a full-scale signal applied to b channel (a in b2). specifications subject to change without notice.
rev. a ad10200 C4C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad10200 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1, 2 v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v analog inputs . . . . . . . . . . . . . . . . . . . . . . . . 5 v p-p(18 dbm) digital inputs . . . . . . . . . . . . . . . . . . . ?.5 v to v dd + 0.5 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature . . . . . . . . . . . . . . . . ?5 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . ?5 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . . 175 c maximum case temperature . . . . . . . . . . . . . . . . . . . . 150 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. 2 typical thermal impedances for ??package: jc = 2.22 c/w; ja = 24.3 c/w. explanation of test levels test level i. 100% production tested. ii. 100% production tested at 25 c and sample tested at specific temperatures. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at 25 c; guaranteed by design and characterization testing for industrial temperature range. table i. output coding (vref = 2.5 v) (two? complement) code a in (v) digital output +2047 +1.024 0111 1111 1111 0 0 0000 0000 0000 ? ?.00049 1111 1111 1111 ?048 ?.024 1000 0000 0000 ordering guide model temperature range package description package option ad10200bz ?0 c to +85 c (case) 68-lead ceramic leaded chip carrier z-68b 5962-9961002hxa ?0 c to +85 c (case) 68-lead ceramic leaded chip carrier z-68b 5962-9961001hxa ?5 c to +125 c (case) 68-lead ceramic leaded chip carrier z-68b ad10200/pcb evaluation board with ad10200bz
rev. a ad10200 C5C pin configuration 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 21 27 43 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 961 8 7 6 5 68 67 66 65 64 63 62 4321 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 pin 1 identifier top view (not to scale) agndb agndb dnc dnc ref_b_out agndb encodeb agnda agnda dnc agnda av cc dnc agnda nc = no connect encodea encodea agnda dv cc encodeb agndb dv cc d0b (lsb) agnda agnda nc agnda dnc vref_a_out dnc dnc av cc agndb agndb ad10200 dnc a in a2 agndb shield nc a in b2 (msb) d11a d10a d9a d8a d7a dgnda d1b d2b d3b d4b d5b dgndb dgnda d6a d5a d4a d3a d2a d1a (lsb) d0a agnda agndb (msb) d11b d10b d9b d8b d7b d6b dgndb pin function descriptions pin no. mnemonic function 1 shield internal ground shield between channels 2, 5, 9?1, 13, 16, 19, 35 agnda a channel analog ground. a and b grounds should be connected as close to the device as possible. 3 vref_a_out a channel internal voltage reference 6, 62 nc no connection 7a in a2 analog input for a side adc 4, 8, 12, 15, 57, 58, 64, 67 dnc do not connect 14, 66 av cc analog positive supply voltage (nominally 5.0 v) 17 encodea complement of encode 18 encodea data conversion initiated on the rising edge of encode input. 20 dv cc digital positive supply voltage (nominally 3.3 v) 21?5, 28?4 d11a?7a, digital outputs for adc a. d0 (lsb) d6a?0a 26, 27 dgnda a channel digital ground 36, 52, 55, 59?1, 65, 68 agndb b channel analog ground. a and b grounds should be connected as close to the device as possible. 37?2, 45?0 d11b?6b, digital outputs for adc b. d0 (lsb) d5b?0b 43, 44 dgndb b channel digital ground 51 dv cc digital positive supply voltage (nominally 3.3 v) 53 encodeb data conversion initiated on rising edge of encode input. 54 encodeb complement of encode 56 vref_b_out b channel internal voltage reference 63 a in b2 analog input for b side adc
rev. a ad10200 C6C definition of specifications analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point on the rising edge of the encode command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential nonlinearity the deviation of any code from an ideal 1 lsb step. encode pulsewidth/duty cycle pulse width high is the minimum amount of time that the encode pulse should be left in logic ??state to achieve rated performance; pulsewidth low is the minimum time encode pulse should be left in low state. at a given clock rate, these specs define an acceptable encode duty cycle. harmonic distortion the ratio of the rms signal amplitude to the rms value of the worst harmonic component. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a ?est straight line determined by a least square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency drops by no more that 3 db below the guaranteed limit. maximum conversion rate the encode rate at which parametric testing is performed. output propagation delay the delay between the 50% point of the rising edge of encode command and the time when all output data bits are within valid logic levels. overvoltage recovery time the amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale. power supply rejection ratio the ratio of a change in output offset voltage to a change in power supply voltage. signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set a 1 db below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. [may be reported in dbc (i.e., degrades as signal levels is lowered) or in dbfs (always related back to converter full scale)]. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set a i db below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. [may be reported in dbc (i.e., degrades as signal levels is lowered) or in dbfs (always related back to converter full scale).] spurious-free dynamic range the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious compo- nent may or may not be a harmonic. [may be reported in dbc (i.e., degrades as signal levels is lowered) or in dbfs (always related back to converter full scale).] transient response the time required for the converter to achieve 0.02% accu- racy when a on e-half full-scale step function is applied to the analog input. two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dbc. voltage standing-wave ratio (vswr) the ratio of the amplitude of the elective field at a voltage maxi- mum to that at an adjacent voltage minimum.
rev. a C7C ad10200 typical performance characteristics frequency ?mhz 0 130 db 20 80 100 110 120 40 60 0 10 30 90 50 70 5 101520253035404550 encode = 105 msps a in = 10mhz (?dbfs) snr = 66.84dbfs sfdr = 82.28dbc tpc 1. single tone @ 10 mhz frequency mhz 0 130 db 20 80 100 110 120 40 60 0 10 30 90 50 70 5 101520253035404550 encode = 105 msps a in = 71mhz ( 1dbfs) snr = 66.04dbfs sfdr = 79.71dbc tpc 2. single tone @ 71 mhz frequency mhz 0 130 db 20 80 100 110 120 40 60 0 10 30 90 50 70 5 101520253035404550 encode = 105 msps a in = 121mhz ( 6dbfs) snr = 66.9dbfs sfdr = 65.57dbc tpc 3. single tone @ 121 mhz frequency mhz 0 130 db 20 80 100 110 120 40 60 0 10 30 90 50 70 5 101520253035404550 encode = 105 msps a in = 41mhz ( 1dbfs) snr = 66.06dbfs sfdr = 80.59dbc tpc 4. single tone @ 41 mhz frequency mhz 0 130 db 20 80 100 110 120 40 60 0 10 30 90 50 70 5 101520253035404550 encode = 105 msps a in = 121mhz ( 1dbfs) snr = 64.92dbfs sfdr = 64.73dbc tpc 5. single tone @ 121 mhz frequency mhz 0 130 db 20 80 100 110 120 40 60 0 10 30 90 50 70 5 101520253035404550 encode = 105 msps a in = 201mhz ( 10dbfs) snr = 66.84dbfs sfdr = 64.57dbc tpc 6. single tone @ 201 mhz
rev. a ad10200 C8C frequency mhz 0 130 dbc 20 80 100 110 120 40 60 0 10 30 90 50 70 5 10152025 3035404550 encode = 105 msps a in = 37mhz & 38mhz ( 10dbfs) sfdr = 79.84dbc tpc 7. two-tone @ 37 mhz/38 mhz frequency mhz 0 130 dbc 20 80 100 110 120 40 60 0 10 30 90 50 70 5 101520253035404550 encode = 105 msps a in = 120mhz & 121mhz ( 7dbfs) sfdr = 63.8dbc tpc 8. two-tone @ 120 mhz/121 mhz 3 3 lsb 0 2 2 0 1 1 512 1024 1536 2048 2560 3072 3584 4096 encode = 105 msps inl max = 0.874 codes inl min = 0.895 codes tpc 9. integral nonlinearity frequency mhz 0 130 dbc 20 80 100 110 120 40 60 0 10 30 90 50 70 5 101520253035404550 encode = 105 msps a in = 71mhz & 72mhz ( 7dbfs) sfdr = 74.8dbc tpc 10. two-tone @ 71 mhz/72 mhz 3.0 1.0 lsb 1.5 0.5 0.0 0.5 2.5 0 1.0 2.0 512 1024 1536 2048 2560 3072 3584 4096 encode = 105 msps dnl max = 0.486 codes dnl min = 0.431 codes tpc 11. differential nonlinearity 0 10 dbfs 6 9 2 3.0 8 4 32.7 62.4 92.1 121.8 151.5 181.2 210.9 240.6 mhz 270.3 300.0 1 7 3 5 encode = 105 msps 3db = 261mhz tpc 12. gain flatness
rev. a ad10200 C9C 10mhz = 50.22 + j.173 50mhz = 48.79 j4.2 100mhz = 46.95 j5.9 150mhz = 48.55 j4.66 tpc 13. input impedance s11 1 3.0 32.7 62.4 92.1 121.8 151.5 181.2 210.9 240.6 mhz 270.3 300.0 10mhz = 1.0149 50mhz = 1.085 100mhz = 1.130 150mhz = 1.092 2 3 4 5 6 7 8 9 10 11 tpc 14. voltage standing wave ratio (vswr) t pd ain encode encode d11 d0 sample n 1 sample n sample n+10 sample n+11 sample n+9 sample n+1 1/f s data n 11 data n 10 n 9 data n 1 data n data n + 1 t v n 2 figure 1. timing diagram v cc 17k 8k 100 100 17k 8k encode encode figure 2. equivalent encode input circuit v cc 100 digital output figure 3. equivalent digital output circuit v cc q1 npn v ref output v cc 6
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v cc a in 7k 50 7k 5k 5k figure 5. equivalent analog input circuit
rev. a ad10200 C10C application notes theory of operation the ad10200 is a high-dynamic range dual 12-bit, 105 mhz subrange pipeline converter that uses switched capacitor architecture. the analog input section uses a in a2/a in b2 at 2.048 v p-p with an input impedance of 50 ? . the analog input includes an ac-coupled wide-band 1:1 transformer, which provides high-d ynamic range and snr while maintaining vswr and gain flatness. the adc includes a high-bandwidth linear track/ hold that gives excellent spurious performance up to and beyond the nyquist rate. the high-bandwidth track/hold has a low jitter of 0.25 ps rms, leading to excellent snr and sfdr performance. ac-coupled differential pecl/ecl encode inputs are recom- mended for optimum performance. using the ad10200 encode input any high speed a/d converter is extremely sensitive to the quality of the sampling clock provided by the user. a track/hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the a/d output. for that reason, considerable care has been taken in the design of the encode input of the ad10200, and the user is advised to give commensurate thought to the clock source. the encode input are fully ttl/cmos compatible. for opti- mum performance, the ad10200 must be clocked differentially. note that the encode inputs cannot be driven directly from pecl level signals (v ihd is 3.5 v max). pecl level signals can easily be accommodated by ac coupling as shown in figure 6. good performance is obtained using an mc10el16 in the circuit to drive the encode inputs. gnd 510 510 0.1 f 0.1 f pecl gate encode encode ad10200 figure 6. ac coupling to encode inputs encode voltage level definition the voltage level definitions for driving encode and encode in differential mode are shown in figure 7. encode inputs differential signal amplitude (v id ) 500 mv min, 750 mv nom high differential input voltage (v ihd ) 5.0 v max low differential input voltage (v ild ) 0 v min common-mode input (v icn ) 1.25 v min, 1.6 v nom encode 0.1 f v ihs v ils encode encode v id v ihd v ild v icm figure 7. differential input levels often, the cleanest clock source is a crystal oscillator producing a pure sine wave. in this configuration, or with any roughly symmetrical clock input, the input can be ac-coupled and biased to a reference voltage that also provides the encode. this ensures that the reference voltage is centered on the encode signal. digital outputs the digital outputs are ttl/cmos-compatible and a separate output power supply pin supports interfacing with 3.3 v logic. analog input the analog input is a single ended ac-coupled high performance 1:1 transformer with an input impedance of 50 ? to 105 mhz. the nominal full scale input is 2.048 v p-p. special care was taken in the design of the analog input section of the ad10200 to prevent damage and corruption of data when the input is overdriven. voltage reference a stable and accurate 2.5 v voltage reference is designed into the ad10200 (vrefout). an external voltage reference is not required. timing the ad10200 provides latched data outputs, with 10 pipeline delays. data outputs are available one propagation delay (t pd ) after the rising edge of the encode command (see figure 1). the length of the output data lines and loads placed on them should be minimized to reduce transients within the ad10200; these transients can detract from the converter's dynamic performance. the minimum guaranteed conversion rate of the ad10200 is 10 msps. at internal clock rates below 10 msps, dynamic perf ormance may degrade. therefore, input clock rates below 10 mhz should be avoided. grounding and decoupling analog and digital grounding proper grounding is essential in any high speed, high resolution system. multilayer printed circuit boards (pcbs) are recom- mended to provide optimal grounding and power schemes. the use of ground and power planes offers distinct advantages: 1. the minimization of the loop area encompassed by a signal and its return path. 2. the minimization of the impedance associated with ground and power paths. 3. the inherent distributed capacitor formed by the power plane, pcb insulation and ground plane. these characteristics result in both a reduction of electromagnetic interference (emi) and an overall improvement in performance. it is important to design a layout that prevents noise from cou- pling to the input signal. digital signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. the pcb should have a ground plane covering all unused portions of the component side of the board to pro- vide a low impedance path and manage the power and ground currents. the ground plane should be removed from the area near the input pins to reduce stray capacitance.
rev. a ad10200 C11C layout information the schematic of the evaluation board (figure 8) represents a typical implementation of the ad10200. the pinout of the ad10200 is very straightforward and facilitates ease of use and the implementation of high frequency/high resolution design practices. it is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. all capacitors can be standard high quality ceramic chip capacitors. care should be taken when placing the digital output runs. because the digital outputs have such a high-slew rate, the capacitive loading on the digital outputs should be minimized. circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. internal circuitry buffers the outputs of the adc through a resistor network to el iminate the need to externally isolate the device from the receiving gate. figure 8. evaluation board mechanical layout evaluation board the ad10200 evaluation board (figure 9) is designed to provide optimal performance for evaluation of the ad10200 analog-to-digital converter. the board encompasses everything needed to ensure the highest level of performance for evaluating the ad10200. the board requires an analog input signal, encode clock and power supply inputs. the clock is buffered on-board to provide clocks for the latches. the digital outputs and out clocks are available at the standard 40-pin connectors j1 and j2. power to the analog supply pins is connected via banana jacks. the analog supply powers the associated compone nts and the analog section of the ad10200. the digital outputs of the ad10200 are powered via banana jacks with 3.3 v. contact the factory if additional layout or applications assistance is required.
rev. a ad10200 C12C figure 9a. evaluation board agndb agndb vfu_b sdout_b ref_b agndb encbb encb agndb 3.3vdb d0b (lsb) d1b d2b d3b d4b d5b dgndb agnda agnda sdout_a agnda 5vaa sclk_a agnda encab enca agnda 3.3vda d11a (msba) d10a d9a d8a d7a dgnda agnda agnda a in a1 agnda sdin_a ref_a sclk_b sdin_b 5vab agndb agndb vfu_a a in a2 agndb shield a in b1 a in b2 u1 ad10200 dgnda d6a d5a d4a d3a d2a d1a d0a (lsba) agnda agndb d11b (msbb) d10b d9b d8b d7b d6b dgndb 9 5 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 43 c37 dns agnda agnda j4 sma agnda j3 sma dns agnda (nc) 0.1 f c33 agnda e49 agnda j7 sma agndb j6 sma dns agndb (nc) 5vab_ agndb (nc) agnda lid agnda agndb c36 dns agndb agndb nc 0.1 f c35 agndb e50 agndb encbb encb agndb d0b d1b d2b d3b d4b d5b dgndb c18 0.1 f u17 dgndb dut_3.3vdb d0a dut_3.3vda c10 0.1 f u1 dgnda 5vaa_ c34 0.1 f agnda agnda agnda nc nc agnda encab enca agnda d11a d10a d9a d8a d7a dgnda agnda agnda dgnda d6a d5a d4a d3a d2a d1a d10b d9b d8b d7b d6b dgndb agnda agndb d11b u1 c20 0.1 f agnda 5aa_ u1 c21 0.1 f agndb 5ab_ l3 47 20% @100mhz c3 10 f agnda 5aa e6 dut_3.3vda l1 47 20% @100mhz u1 c12 0.1 f dgnda c29 10 f 3.3vda e25 l4 47 20% @100mhz c4 10 f agndb 5ab e5 dut_3.3vdb l2 47 20% @100mhz u8 c16 0.1 f dgndb c30 10 f 3.3vdb e26 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 dgnda h40dm j1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (msb) b11a b10a b9a b8a b7a b6a b5a b4a b3a b2a b1a (lsb) b0a f3a f2a f1a f0a dgnda r71 50 buflata c15 10 f dgnda 3.3vda 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 dgndb h40dm j2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (msb) b11b b10b b9b b8b b7b b6b b5b b4b b3b b2b b1b (lsb) b0b f3b f2b f1b f0b dgndb r72 50 buflatb c14 10 f dgndb 3.3vdb 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 r18 100 b11b (msb) r17 100 b10b oe2 o15 o14 gnd o13 o12 vcc o11 o10 gnd o9 o8 o7 o6 gnd o5 o4 vcc o3 o2 gnd o1 o0 oe1 u17 74lcx16374 le2 i15 i14 gnd i13 i12 vcc i11 i10 gnd i9 i8 i7 i6 gnd i5 i4 vcc i3 i2 gnd i1 i0 le1 dut_3.3vdb dgndb dgndb dgndb dut_3.3vdb dgndb dgndb dgndb r16 100 b9b r45 100 b6b r46 100 b5b r14 100 b3b r40 100 b8b r44 100 b7b r15 100 b4b r13 100 b2b r24 100 b1b (lsb) r23 100 b0b r22 dns f3b r20 dns f1b r21 dns f2b r19 dns f0b dgndb dgndb dgndb dgndb dut_3.3vdb (lsb) d0a d1a d2a d3a d4a d5a d6a d7a d8a d9a d10a d11a dut_3.3vdb r53 0 r54 0 r49 0 r50 0 dgndb r8 50 latchb 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 r18 100 b11a (msb) r17 100 b10a oe2 o15 o14 gnd o13 o12 vcc o11 o10 gnd o9 o8 o7 o6 gnd o5 o4 vcc o3 o2 gnd o1 o0 oe1 u16 74lcx16374 le2 i15 i14 gnd i13 i12 vcc i11 i10 gnd i9 i8 i7 i6 gnd i5 i4 vcc i3 i2 gnd i1 i0 le1 dut_3.3vda dgnda dgnda dgnda dut_3.3vda dgnda dgnda dgnda r16 100 b9a r45 100 b6a r46 100 b5a r14 100 b3a r40 100 b8a r44 100 b7a r15 100 b4a r13 100 b2a r24 100 b1a (lsb) r23 100 b0a r22 dns f3a r20 dns f1a r21 dns f2a r19 dns f0a dgnda dgnda dgnda dgnda dut_3.3vda (lsb) d0a d1a d2a d3a d4a d5a d6a d7a d8a d9a d10a d11a dut_3.3vda r52 0 r51 0 r47 0 r48 0 dgnda r7 50 latcha nc = no connect
rev. a ad10200 C13C dgnda e42 e44 e48 e67 e70 e72 e73 e76 e81 e41 e43 e47 e68 e69 e71 e74 e75 e82 agnda e65 e66 dgndb e36 e38 e40 e79 e84 e35 e37 e39 e80 e83 agndb e29 e30 e46 e45 so2 so5 so3 so6 so1 so4 stand offs on the board e33 dgndb dgndb dgndb e3 e4 agndb agnda e34 dgnda dgnda dgnda banana jacks for gnds and pwrs 2 in +5vaa_ err sd nr out 1 u14 3 adp3330 5 6 sd 4 nc d db vbb vcc q qb vee mc10el16 u2 8 7 6 5 1 2 3 4 agnda r56 33k r58 33k dgnda c6 0.1 f r3 100 dgnda nc d db vbb vcc q qb vee u3 8 7 6 5 1 2 3 4 dgnda +3.3va r4 100 dgnda r41 50 agnda j12 sma c2 0.1 f c1 0.1 f r1 50 agnda j5 encode sma agnda c13 0.47 f agnda +3.3va agnda r42 100 r43 100 encab encab c7 0.1 f c8 0.1 f agnda d0 d0b d1b d1 vcc q0 q1 vee mc100ept23 8 7 6 5 1 2 3 4 dgnda +3.3va c5 0.1 f dgnda e23 e19 latcha buflata u4 1 2 in +5vab_ err sd nr out 1 u15 3 adp3330 5 6 sd 4 nc d db vbb vcc q qb vee mc10el16 u11 8 7 6 5 1 2 3 4 agndb r38 33k r39 33k dgndb c25 0.1 f r3 100 dgnda nc d db vbb vcc q qb vee mc10el16 8 7 6 5 1 2 3 4 dgndb +3.3vdb r66 100 dgndb r61 50 agndb j11 sma c23 0.1 f c22 0.1 f r60 50 agndb j10 encode sma agndb c27 0.47 f agndb +3.3vb agndb r63 100 r64 100 encbb encb c24 0.1 f c28 0.1 f agndb d0 d0b d1b d1 vcc q0 q1 vee mc100ept23 8 7 6 5 1 2 3 4 dgndb +3.3vb c26 0.1 f dgndb e24 e22 latchb buflatb u10 2 nc = no connect nc = no connect mc10el16 u9 figure 9b. evaluation board
rev. a ad10200 C14C bill of materials list for ad10200 eval board qty. component name ref des value description m/s p/ns 2 74lcx16373mtd u16, u17 74lcx16374mtd (fairchild) 1 ad10200bz u1 ad10200bz 2 adp3330 u14, u15 sm 3.3 v regulator adp3330art-3.3-rl7 (analog) 4 bres0805 r38, r39, r56, r58 33 k ? sm 0805 resistor erj6geyj333v (panasonic) 4 bres0805 r1, r41, r60, 50 ? sm 0805 resistor erj6geyj510v (panasonic) r61 8 bres0805 r3, r4, r42, r43, 100 ? sm 0805 resistor erj6geyj101v (panasonic) r63, r64, r65, r66 23 cap2 c1, c2, c5, c6, 0.1 f sm 0805 capacitor grm40x7r104k025bl c7, c8, c9, c10, (mena) c12, c16, c17, c18, c20, c21, c22, c23, c24, c25, c26, c28, c33, c34, c35 4 cap2 c13, c27, c38, c39 0.47 f sm 1206 capacitor vj1206u474mfxmb (vitramon) 2 n49dm j1, j2 2 20 100 male connector tsw-120-08g-d (samtec) 4 ind2 l1, l2, l3, l4 47 ? inductor 2743019447 (fair ride) 4 mc10el16 u2, u3 u9, u11 mc1016ep16d (motorola) 10 bjack bj1 ?bj10 power jack 108-0740-001 (johnson comp.) 2 mc100elt23 u4, u10 sy100elt23l (micrel-synergy) 6 polcap2 c3, c4, c14, c15, 10 f sm 1812 polar capacitor t491c106m016a57280 c29, c30 (kemet) 8 res2 r47, r48, r49, 0 ? sm 0805 resistor erj-6gey0r00v (panasonic) r50, r51, r52, r53, r54 4 res4 r7, r8, r71, r72 50 ? sm 0805 resistor erj-6geyj510v (panasonic) 24 res2 r9, r10, r11, r12, r13, r14, r15, r16, r17, r18, r23, r24, r25, r26, r27, r28, r29, r30, r35, r36, r40, r44, r45, r46 1 sma j4 a in a2 142-0701-201 (johnson comp.) 1 sma j7 a in b2 142-0701-201 (johnson comp.) 2 sma j11, j12 encode 142-0701-201 (johnson comp.) 2 sma j5, j10 encode 142-0701-201 (johnson comp.) 4 stand-off s01?04 stand-off 313-2477-016 (johnson comp.) 4 screws screws (stand-off) mpms 0040005ph (building fasteners) 1 pcb ad10200 eval board gs03363 rev. a
rev. a ad10200 C15C figure 10a. bottom view

figure 10b. bottom assembly
rev. a ad10200 C16C figure 10c. ground 1 figure 10d. ground 2
rev. a ad10200 C17C

figure 10e. bottom silk figure 10f. top view
rev. a ad10200 C18C

!"" " ! "#$ %! &! &! %! $ $ figure 10g. top assembly

!"" " ! "#$ %! &! &! %! $ $ figure 10h. top silk
rev. a C19C ad10200 outline dimensions dimensions shown in inches and (mm). 68-lead ceramic leaded chip carrier (z-68b) toe down angle 0 8 degrees detail a 1.190 (30.23) 1.180 (29.97) sq 1.170 (29.72) top view (pins down) pin 1 10 26 9 61 60 43 27 44 0.800 (20.32) bsc 0.960 (24.38) 0.950 (24.13) sq 0.940 (23.88) 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) 0.021 (0.533) 0.017 (0.432) 0.014 (0.357) 0.230 (5.84) max 0.290 (7.37) max detail a 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) 0.060 (1.52) 0.050 (1.27) 0.040 (1.02) 1.070 (27.18) min revision history location page data sheet changed from rev. 0 to rev. a. edit to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edit to figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 edit to encode inputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 edit to figure 9a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
C20C c01634C0-8/01(a) printed in u.s.a.

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